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eDV-Hera: Efficient data processing on heterogeneous hardware


Microproject in cooperation with SAP, funded by the German Ministry of Science and Education in the context of the “Software Campus” program.

One of the primary challenges when trying to exploit the capabilities of modern hardware to accelerate data processing tasks is the high diversity of available architectures. Modern computer systems often feature multiple different (co-)processors - including multi-core CPUs, graphics cards, or FPGAs -, differing substantially in their micro-architectures, computational models, memory connections, etc. Writing programs that can fully utilize such different resources is a highly work-intensive process that requires both detailed knowledge about the program structure and the utilized algorithms, as well as an substantial familarity with all to-be-supported hardware architectures. This process leads to a sharp increase in development and maintenance costs, which is why modern systems exploit the additional computational power of coprocessors only in certain specialized settings to process data. Looking at the projections of experts, which expect that in the near future highly heterogeneous hardware architectures will become the norm not the exception, reducing this development overhead will become highly important.

The primary goal of eDV-Hera is to address this problem by developing methods and technologies that aim at reducing the development effort to write efficient data processing programs that can fully utilize heterogeneous hardware architectures. This is done by strictly following a so-called “hardware-oblivious” approach: Developers specify their programs in an abstract, declarative form that does not include any hardware-specific adjustments. Based on this specification, the system automatically generates code at runtime that is optimized to efficiently utilize the available hardware configuration. This automatic code generation will be backed by self-learning methods, which automatically deduce specific code optimization techniques for a given hardware architecture by observing the runtime behaviour of existing programs.

The two-year project is carried out in cooperation with SAP and is funded by the German Ministry of Science and Education in the context of the “Software Campus” program.

For further details regarding the “Software Campus”, please refer to: http://www.softwarecampus.de/en/home/

Further information regarding the cooperation partner SAP can be found at: http://www.sap.com/index.html

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