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TU Berlin and DFKI Research Paper Accepted for Publication in PVLDB Vol. 14

The Paper “Scotch: Generating FPGA-Accelerators for Sketching at Line Rate” by Martin Kiefer, Ilias Poulakis, Sebastian Breß and Volker Markl will be featured in Proceedings of the VLDB Endowment (PVLDB), Volume 14, Issue 3.

In their paper, the authors propose Scotch, a novel system for accelerating sketch maintenance using the custom FPGA hardware. Scotch provides a domain-specific language for the user-friendly, high-level definition of a broad class of sketching algorithms. A code generator performs the heavy-lifting of hardware description, while an auto-tuning algorithm tunes the summary size. Our evaluation shows that FPGA accelerators generated by Scotch outperform CPU- and GPU-based sketching by up to two orders of magnitude in terms of throughput and up to one order of magnitude in terms of energy efficiency.

To learn more about PVLDB, please visit http://vldb.org/pvldb/ [1]

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